Design and Implementation of C-Band Frequency Synthesizer Using LMX2592 IC

: The paper presents the design scheme and implementation of a PLL-based-frequency synthesizer using LMX2592 IC. The frequency synthesizer have vital role in the development of up-converter and down-converter equipments. Therefore, on the RT-Duroid RO4350 substrate, a low phase noise and stable carrier generator is designed and implemented. Graphical User Interface (GUI) & LAN based programming is developed to easily change the synthesizer frequency. The control system analysis using root locus and bode plot is presented for system stability. The experimental results representing the performance parameters, like frequency range, frequency step size, output power, phase noise, carrier stability, harmonics, and spurious, etc., are also presented in the paper. The analysis of spurious and phase noise performance at near integer boundary conditions are done by changing loop bandwidth and phase margin.


Introduction
The microwave has been broadly employed in numerous domains.The significant applications of microwaves include millimeter wave communications, radar, tracking, guidance, electronic warfare, and other areas (Skolnik, 2002;Crosson, Limaye, & Laymon, 2010;Ma, Wang, & Li, 2012;Yu, Xu, & Shen, 2012).The frequency synthesizer is a vital entity of any communication equipment.The frequency synthesizer behavior can instantly impact the wave-sending and receiving system quality.The phase-locked loop-based frequency synthesizer performs well with higher resolution frequency and broader bandwidth than different frequency synthesizing systems (Gao, & Gao, 2010;Zhu, & Wang, 2015;Tsai, Hsu, & Chao, 2015).The frequency band, phase noise, power output, spurious and harmonics are critical performance parameters of the frequency synthesizer.
Phase locked loop is an integrated-signal electronic circuit.It is mainly implemented with radio frequency (RF) and digital & analog codesign building blocks.The PLL is a non-linear negative feedback closed-loop control system.A PLL consists of a phase detector, loop filter, and voltage-controlled oscillator that locks the VCO phase to a reference signal.PLLs are used in many applications, including generating a clean, tunable, and stable reference frequency.It is also used in other applications, including a clock recovery circuit for high-speed communication, frequency modulation (FM) and demodulation, The frequency synthesizers are used in many test and measurement equipment, defence and RADAR, cell phones, walkie-talkies, satellite receivers, etc. Frequency synthesizer stability and accuracy depend on the reference source; therefore, a temperature-compensated crystal oscillator is used as stable reference source input to the PLL.A frequency synthesizer generates a range of frequencies from a single reference frequency.In the frequency synthesis process, a new frequency is derived from a reference frequency by combining various additions, subtractions, multiplications, and divisions (Pandit, Deepak, & Basu, 2014).

Suggested Citation
The frequency synthesizer is widely classified into direct and indirect synthesizers.The direct forms of frequency synthesizer are implemented by creating a waveform directly without any form of frequency transforming element.The direct synthesizer is additionally sub-classified into direct analogue frequency synthesis (DAFS) and direct digital frequency synthesis (DDFS) (Kroupa, 2003).DAFS requires a lot of circuitry (integrate a mixer, filter, etc.) and is also called a mix-filter-divide architecture.The switching time performance of DAFS is excellent but consumes more power due to extensive circuitry.DDFS has a tiny resolution, excellent frequency switching time, and low phase noise.However, it has narrow output frequency range and has significant spurious components (Yang, Cai, & Lianfu, 2011).The indirect frequency synthesizer is based on PLL technology, where the output signal is generated indirectly.The VCO output is indirectly controlled by a lowfrequency stable reference to obtain a highly stable output frequency.PLL frequency synthesizer has a broad output frequency range compared to the above schemes and significantly suppresses spurious signals.
The PLL-based frequency synthesizer in C-band will be used in the in-house development of upconverter and down-converter equipment.
The paper is organized into five different sections including the introductory Section 1.In Section 2, the C-band frequency synthesizer design principle is given.In Section 3, loop filter parameters & phase noise simulation results obtained from PLLatinum Sim software and control system analysis are discussed.In Section 4, detailed test & evaluation results for different performance parameters are given.Finally, we conclude Section 5.

C-Band Frequency Synthesizer: The Design Principle
This section discusses the specifications of the C-band frequency synthesizer, LMX2592 chip principles, system architecture & the device selection, schematic diagram, and software implementation.

Specifications of C-Band Frequency Synthesizer
The specifications of the C-Band frequency synthesizer are given in below Table 1.The phase-lock loop (PLL) consists of a Sigma-Delta modulator (1st to 4th order) for fractional N-divider values.The fractional denominator is programmable to 32-bit long, allowing a very fine resolution of frequency step.The device requires a typical single 3.3 V supply voltage and 250 mA (for a single 6-GHz, 0 dBm output) total current consumption.LMX2592 internal block diagram is described in Figure 1, which consists of a programmable input path divider, programmable N divider, sigma-delta modulator, channel divider, phase frequency detector, charge pump, etc. (Wideband PLLatinum, 2015).The phase noise of the VCO is degraded by a factor of 20 10 () compared to the reference source; N is the desired frequency ratio to the reference frequency (Chenakin, 2010).As per system architecture and specifications, the reference frequency is 100 MHz.A temperaturecompensated crystal oscillator (TCXO-TX550) of 100 MHz made by VECTRON is selected as an onboard reference source.The phase noise specification is -130 dBc/Hz @ 1 kHz offset.If the onboard reference source fails, a 10 MHz symmetricom rubidium frequency standard is chosen as an external reference source.The default output of the rubidium frequency standard is a sine waveform, so LT1715-4 ns 150 MHz dual comparator circuit is used to convert the sine wave into a square waveform.The LT1715 is an ultra-fast dual comparator enhanced for low-voltage operation.It used distinct input and output power supplies to enable independent analog input ranges and output logic levels with no performance loss.The output from the rubidium source is connected to the non-inverting input of the above-discussed comparator, and the inverting input is grounded.
For the selection of internal and external reference sources, a 2:1 multiplexer circuit ADG3257 is used.The ADG3257 is a highspeed mux containing four 2:1 multiplexers.It provides low power dissipation, high impedance outputs, low on-resistance (2 Ω), and high switching speed.It allows the inputs to be connected to the outputs without adding propagation delay or generating additional ground bounce noise.A single pole double throw (SPDT) mechanical switch provides the multiplexer's select signal (Low or High).
The 3 dB bandwidth of the third order loop filter has a sharper cut-off than that of the secondorder and the associated noise will be less.However, a third order loop will be only required if there is a continuous step change in frequency due to programming the N divider block, which is required only for frequency tracking applications.Here since Frequency Synthesis is the desired application, the steady state gain persisting for the duration of setting the required frequency is very less, second-order loop filter is sufficient for synthesis applications.
An RF amplifier from Analog Devices HMC392ALC4 (GaAs MMIC Low Noise Amplifier) is chosen to increase the signal strength at the output of VCO.The amplifier frequency range is from 3.5 to 8 GHz.It provides a typical gain of 17 dB, 3 dB maximum Noise Figure (NF), and minimum 16 dBm output power for 1 dB compression (P1dB).The supply voltage can range from 2 to 5.5 V (+3.3 V is used).The RF input (RFIN) and output (RFOUT) ports are DC-blocked and matched to 50 Ω for ease of use.
The The whole system architecture of the C-band frequency synthesizer with SPI interfacing from Raspberry Pi 3B to the Synthesizer is shown in Figure 2.

Principle of Operation
The frequency synthesizer working principle is that the reference signal   passes through the input path.A frequency doubler and divider/multiplier (scaler) are the components of the input path.The reference signal of the phase frequency detector, also known as the frequency of the phase frequency detector   , is the signal that is passed through the input path.After passing via the VCO doubler or direct, the VCO signal reaches the pre-scaler, N divider, and is transformed into   .The phase frequency detector (PFD), also known as the PLL phase detector, compares   and   and employs the charge pump to generate a correction current until the two signals are in phase (the PLL is locked).The correction current pulses from the charge pump output are converted into a DC control voltage and applied to the tuning voltage (Vtune) of the VCO by the use of external components (loop filter) (Wang, 2017).

Graphical User Interface (GUI) Development
The frequency synthesizer card based on LMX2592 is connected to the Serial Peripheral Interface (SPI) control pins of a Raspberry Pi 3B Board, which is intended to be the functional controller for the Synthesizer.
Raspberry Pi 3B acts as the SPI Master to enable the flow of control signals and data to & from the LMX2592.The register sets to be programmed onto LMX2592 for the desired synthesizer operation is calculated via a python based program after accepting relevant inputs from the user.A web-based Graphical User Interface application is developed and hosted on a web-server on the Raspberry Pi 3B itself and is designed to have low-latency, less overhead and high throughput, running on the secure http interface.
The Web Interface allows user to input the required fields such as Mode Selection, Frequency selection, Output section selection, RF enable etc. and the same is validated before getting processed for the register calculation program.
The features of such a GUI are: Instantaneous control of synthesizer operation and changeover between modes, RF on/off feature, RF Output port control, network-wide availability of the application through simple web browser(no need of installation of additional software), continuous monitoring of lock status of the Synthesizer PLL, Error handling at user input level for all parameters etc.

Mode: Set Frequency Mode
In this mode, the user enters the frequency of his choice (within C-Band range) for synthesis and selects the output port (RF_A or RF_B or RF_AB).

Figure 4. Set Frequency Mode
Based on user inputs and pressing the proceed button, the Raspberry Pi 3B gathers the user requirement and calculates registers accordingly, transmits the calculated register set to the LMX2592 over SPI.The PLL lock status is monitored through a readout register from LMX2592, which is displayed in real-time on the GUI.
RF On/Off button can be used to start/stop the RF power at output ports as per user requirement.

Mode: Continuous Sweep Mode
In this mode the user enters Start and Stop the frequencies of his choice (both must be within C-Band range) for continuous sweeping signal at an incremental step frequency and step delay of their choice.The provision of selecting the output port (RF_A or RF_B or RF_AB) is also provided.

Figure 5. Continuous Sweep Mode
The Raspberry Pi 3B then continuously calculates the required frequency and corresponding register set, transmits it to the LMX2592 over SPI in a loop with incremental frequency change after the selected step delay.
The PLL lock status is also continuously monitored for each incremental frequency through a readout register from LMX2592 which is displayed in real-time on the GUI.
RF On/Off button can be used to momentarily stop the RF power at the output ports and then resume sweeping from the exact same frequency previously stopped at.

Mode: Single Sweep Mode
This mode is similar to continuous sweep mode except that the frequencies are swept over the user-defined range only once.Upon completing the full range sweep, last frequency in the range will persist at the selected output.
RF On/Off button can be used to pause the sweep momentarily and can be resumed any point of time to reach the stop frequency and persist at the same frequency.
In the realization process, the four General Purpose Input/output (GPIO) ports of Raspberry Pi 3B are connected with the four control pins of LMX2592.LMX2592 contains Chip Select Bar (CSB pin 24), Serial Clock (SCK pin 16), Serial Data in (SDI pin 17), and Serial Data Out/Lock Detect (SDO/LD pin 20) as serial interface control pins.The CSB pin is for SPI chip select bar or uWire latch enable (LE), and the SCK pin is for the serial clock input.The SDI pin is for serial data input, and the SDO/LD pin, which is for serial data output or lock detection, can output different internal signals through the configuration of internal registers.The interface information for four control signals from the Raspberry Pi 3B to the LMX2592 IC is provided in Table 2. 24-bit shift registers are used for programming.An R/W bit (MSB), a 7-bit address field, and a 16-bit data field make up the shift register.In the R/W (bit 23), 0 indicates a write and 1 a read.The internal register address is decoded by the address field ADDRESS (bits 22-16).The data field DATA comprises the remaining 16 bits (bits15:0).Serial data is sent into the shift register on the rising edge of the clock while CSB is low (data is programmed MSB first).Data is moved from the data field into the chosen register bank when the CSB signal is strong.

Loop Filter Parameters & Phase Noise Simulation And Control System Analysis
In this section, loop filter parameters & phase noise simulation results obtained from PLLatinum Sim software and control system analysis are discussed.

Loop Filter Parameters and Phase Noise Simulation
The spurious high-frequency signal is suppressed by a loop filter, which is a low-pass filter.Furthermore, it is crucial to the system's stability and phase noise components.Depending on their design, loop filters can be active or passive.The amplifier gain in the active filter introduces noise into the system.Hence the phase noise performance of the PLL created by the passive filter is better than that of the PLL with the active filter (Wang, 2017).This design's tuning voltage range of the LMX2592 is 0 to 2.5 V.The range of the output voltage at the loop filter output (  ) is sufficient for the range of the VCO tuning voltage.Therefore, the passive filter should be taken into account.
The software PLLatinum Sim PLL design can be helpful when designing the loop filter.Designing the loop filter requires a few key parameters.They are the charge pump current   , loop bandwidth (BW), phase margin, VCO tuning sensitivity   , and filter design (active or passive; order).The closed-loop bandwidth of the loop is typically 1/10 or 1/20 of the reference frequency so that good phase noise performance can be achieved.It can be smaller (Wang, 2017) for better phase noise.The design of this external loop filter has a loop bandwidth of around 100 kHz.The loop phase margin must be in the system's stable zone to meet stability requirements.Here 72 degrees is selected except near the integer boundary (generally greater than 40 degrees is the best phase margin).These parameters are finalized based on software simulation results and same is verified during detailed test & evaluation.After optimization, the loop filter simulation parameters are  1 = 6.8 nF,  2 = 270 nF, and  2 = 39 Ω.In real circuit design, we usually select similar capacitance and resistance values.The impedance of the loop filter, which can be represented as follows (Banerjee, 2017), provides the transfer function for this secondorder loop filter.

𝐹𝐹(𝑠𝑠) =
() Where,   is voltage across the loop filter and   is the current coming from the charge pump.After simplification of the above equation, we get (2) Where, Substitute Equations ( 4) and ( 5) in equation ( 3  The phase noise performance is simulated using the software, which can be seen in Figure 7.The total phase noise is -92.7dBc/Hz@1kHz offset at 6500MHz.

Control System Analysis
The phase-locked loop is a closed-loop control system, and the stability of this will affect the performance of the frequency synthesizer.For this purpose, control system analysis is required, and stability can be defined based on the location of poles in the root locus plot.The other method of system stability can be obtained from Bode-Plot phase margin information.

Test And Evaluation (T&E) Results
The summary of the test and evaluation results of the C-band frequency synthesizer is mentioned below in Table 3. Detailed results for ten random frequencies in the frequency range of 4000-6500 MHz are given in Table 4.

Conclusion and Discussion
The frequency synthesizer PCB card has four layers: the top, ground, power, and bottom layer and is realized using base material RO4350 (RT Duroid) Er 3.66, High Tg FR4.PCB card design is based on a single-ended microstrip structure, and trace parameters like width, height, spacing, etc., are selected for achieving a controlled impedance of approximately 50 Ω.In below Figure 12, component marking on PCB top layer is given.

Figure 15. Components Marking on PCB Top Layer
The PLL-based fractional frequency synthesizer in C-band developed using PLL IC LMX2592 has been presented in this paper.On the RT-Duroid RO4350 substrate, a Low Phase Noise carrier generator is designed and implemented utilizing a PLL synthesizer.This implemented model shows frequency accuracy of less than ±1 kHz and the phase noise better than -90 dBc/Hz @ 1 kHz offset.The carrier stability results at different frequencies are within 0.5 dB for 8 hours.The bandpass filter will be added to the amplifier's output to improve harmonics performance.As per Table 5, the C-Band frequency synthesizer's performance meets all required specifications given in Table 1.Hence, it can be used as a local oscillator for the in-house development of up/down converter equipment.
In Table 7, loop bandwidth and phase margin are computed using PLLatinum Sim software for different PFD and charge pump gain values over the frequency synthesizer operating range.As per the analysis, spurious performance can be improved for near integer boundary conditions by reducing phase frequency detector (PFD) frequency and charge pump gain resulting in lower loop bandwidth and phase margin.The trade-off between spurious and phase noise here is that as loop bandwidth & phase margin reduce, spurious performance is improved, and phase noise performance at 10 kHz offset is poorer.

Figure 2 .
Figure 2. System Architecture of C-Band Frequency Synthesizer

Figure 9 .
Figure 9. External Second-Order Passive Loop Filter Figure 10.Simulation Result of Total PhaseNoise @ 6500 MHz

Figure 14 .
Figure 14.Bode Plot Obtained from MATLAB

Figure
Figure 16.Frequency Synthesizer PCB Card on RO4350 substrate

Table 4 . Test and Evaluation Results
*T&E Results for C-